With the advent of Ultra Large Scale Integrated (ULSI) technologies, the sizes of semiconductor devices have gotten smaller and smaller than ever, resulting in the packing density of a wafer being continuously increased.
Metal oxide semiconductor field effect transistors (MOSFETs) have been traditionally used and widely applied in semiconductor technologies. As with the trend of the integrated circuits, the fabrication of the MOSFET also meets various issues such as short channel effect. One of the issues is hot carriers that will inject into gate oxide, which is overcome by the development of lightly doped drain (LDD) structure. Parasitic capacitance is a main reason to degrade the speed of the MOSFET, which also causes high power for operating the devices. Typically, the reasons to generate the parasitic capacitance are the gate capacitance, gate-to-drain overlap capacitance, the junction capacitance and the gate fringing capacitance.
The requirement ofthe ULSI CMOS technology is the need for devices operated at low supply voltage and at a high speed. Thus, to minimizing the parasitic capacitance is a key way to achieve high speed and low power devices for CMOS ULSI devices". See "Impact of Reduction of Gate to Drain Capacitance on Low Voltage Operated CMOS Devices, Kyoji Yamashita et al., 1995, Symposium on VLSI Technology Digest of Technical Papers.". Prior art approaches to overcome these problems have resulted in the development of the gate-side air-gap (GAS) structure to reduce the parasitic capacitance in the MOSFET. Please see "A Gte-side Air-gap Structure (GAS) to Reduce the Parasitic Capacitance in MOSFETs38, M. Togo et al., 1996, Symposium on VLSI Technology Digest of Technical Papers. High speed and low power operation devices are achieved by using the GAS structure in MOSFETs. This effectively reduced the gate fringe capacitance of the MOSFETs. However, it is difficult to reduce the valve of fringing field capacitance (C.sub.FR), due to the difficulty of scaling down the dielectric spacer thickness as scaling down the device dimension. The C.sub.FR becomes more important as the gate length is reduce to deep sub micron-meter range.